Internal MPU clock
Used for bus control during ROM operations, OXXX is TRUE when addresses
A13, A14, and A15 are low
A0 to A15
Airborne Data Annotation System
Clock used to synchronize the transfer of ADAS data
Disables transfer of accumulated video while ADAS data is being received.
ADAS data word ready-one of four basic interrupts
Timing for analog-to-digital output latch-even range bins.
Timing for analog-to-digital output latch-odd range bins
External signal signifying from which side the SLAR antenna is looking.
ANT XTN DET
Antenna transition detector-determines when SLAR is using both antenna
MPU disabled-address bus available
B versus C field video
Binary coded decimal mode-ADAS can be either BCD or numeric data
BITE FT-generates fixed target video during BITE
B GTD 5 MHz
BITE gated 5 MHz-internally generated range bin clock
Built-in test equipment.
Turns on BITE IN PROCESS lamp during BITE test
BITE MT-generates moving target video during BITE
Video data processing is in both antenna mode
Resets BITE request latches
Drift angle data ready-one of four basic interrupts.
28V CONT POWR
Control power signal used to enable primary power relay K1
DO to D7
Video delay information from SLAR
Enables BITE IN PROCESS indicator.
Enables ENCODER ERROR indicator.
FTO to FT4
Data bit representing FT video (FT4 is most significant)
FT data input latch reset