TM 11-5841-287-30
φ2, φ2
Internal MPU clock
OXXX
Used for bus control during ROM operations, OXXX is TRUE when addresses
A13, A14, and A15 are low
A
A0 to A15
Individual microprocessor address bits.
ADAS
Airborne Data Annotation System
ADAS CLOCK
Clock used to synchronize the transfer of ADAS data
ADAS DISABLE
Disables transfer of accumulated video while ADAS data is being received.
ADAS IRF
ADAS interface.
ADAS RDY
ADAS data word ready-one of four basic interrupts
ADLE
Timing for analog-to-digital output latch-even range bins.
ADLO
Timing for analog-to-digital output latch-odd range bins
ANTENNA SELECT
External signal signifying from which side the SLAR antenna is looking.
ANT XTN DET
Antenna transition detector-determines when SLAR is using both antenna
mode
B
BA
MPU disabled-address bus available
B/C
B versus C field video
BCD MODE
Binary coded decimal mode-ADAS can be either BCD or numeric data
B-FT
BITE FT-generates fixed target video during BITE
B GTD 5 MHz
BITE gated 5 MHz-internally generated range bin clock
BITE
Built-in test equipment.
BITE LITE
Turns on BITE IN PROCESS lamp during BITE test
B-MT
BITE MT-generates moving target video during BITE
BOTH ANT
Video data processing is in both antenna mode
BTR RES
Resets BITE request latches
C
CLEAR
Drift angle data ready-one of four basic interrupts.
28V CONT POWR
Control power signal used to enable primary power relay K1
D
DO to D7
Microprocessor data bus bits 0 through 7
DLY (0-50)
Video delay information from SLAR
DRIFT ANG
Drift angle
E
EN BIPL
Enables BITE IN PROCESS indicator.
ENCDR ERROR
Enables ENCODER ERROR indicator.
ENCODER
Indicator
ENCODER FAULT
Indicator
F
FILM SPD
Film speed
FT
Fixed target.
FTO to FT4
Data bit representing FT video (FT4 is most significant)
FT DAINLAR
FT data input latch reset
Glossary-1
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