TM 11-5841-287-30
GLOSSARY-Continued
G
GTD CLOCK
Gated clock
H
HALT, HALT
Signal disables microprocessor for use of DATA BUS by video data processing
Hamming code bits
Three error correcting bits
I
ID
Identifies data as FT or MT video
INT RES
Resets video processing circuits
IWC
Integrated write control signal used to transfer accumulated video into output
memory.
J
K
L
LOAD
Initializes video control circuits and range bin address counters
L/R
6 Hz BITE signal which simulates both antenna operation
M
M10
Most significant address bit on the output memory board
MPU
Microprocessor unit
MT
Moving target
MT DAINLAR
Moving target data Input latch reset
N
NMI
Nonmaskable interrupt sequence initiated
O
OUTBUF IRQ
Output buffer interrupt request sequence initiated
OUTPUTIRECV IRF
Output or receive register fault
P
P
Parity.
PF ERROR
Power fault error signal to enable ENCODER FAULT indicator
PRI
Pulse repetition intervals.
Q
R
RAO to RA10
Range bin address 0 through 10
RAOE to RA1OE
Range bin address 0 through 10 even
RAOO to RA10O
Range bin address 0 through 10 odd
RANGE
Kilometers of displayed radar video.
RANGE DELAY
Kilometers of video not shown from aircraft to first video shown
RC
Read control.
R CLEAR
Range bin clear signal to initialize video accumulation.
RCVR
Receive mode of receiver/transmitter operation
RESET
Master reset line-power-on-reset
RESET XTN DET
Initializes antenna transition detector
RT DATA ERROR
One of the four basic interrupts
R/T FAULT
Indicator
Glossary 2
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