TM 11-5841-287-30
Figure 3-14. Power fault detector 2A13 test point locations.
Control
Setting
Control interface unit
V/division
vertical, and 10 microseconds/division
POWER ON/OFF
OFF
horizontal.
MODE SELECT
POWER OFF
Digital tester
pins 1, 2, 3, 4, 13, 14, 16, and 17 of U31 for digital
POWER
Down (off)
activity
UUT POWER
Down (off)
NOTE
TEST RATE PER SEC
400K
The signals on the pms of U31 are
NUMBER OF TESTS
1M
DISPLAY
PASS/FAIL
irregular. Ensure that both logic levels
PROBE THRESHOLD
2V
occur. A logic "1" is defined as between
c. Test Procedure.
Perform the following
+ 2.4V and + 5 OV A logic "0" is defined
steps in the sequence given. Change equipment control
as between O.OV and + 0.4V
settings only when instructed in the test procedure
(25) Remove the probe tip from the circuit
(1) Verify that cable W3 is connected as
card test point and set the POWER switches on the
equipment to their off positions Remove the circuit card
tested into the MODULE TEST circuit card rack
under test and the program card from the test setup.
connector J1 on the control interface unit.
3-35. Testing Output Memory 2A14
(2) Insert A14 program card no 1 (SM-A-
a. Test Setup Connect the equipment as
942370-1) into the card reader slot on the digital tester
(3) On the control interface unit, set the
b. Preliminary Control Settings Prior to testing
POWER
the circuit card, set the equipment controls as follows
3-43