TM 11-5841-287-30
(2) Input register logic The data to be
meanings are significantly different, the system out-put
formatting is accomplished using the same logic circuitry
transmitted is initially loaded into the first and second
In either case (MT or FT), the 8-bit input for-mat is
word input registers First word register clocking is
converted to the appropriate 11-bit output for-mat by
enabled by the timing and control logic input signals WC
simple redundant connections at the MT/FT gated bus
and 0006 Signals WC and 0007 are used to generate the
driver Again, processing is performed in two word groups
clock for the second-word register The outputs of the
and alternate word polarity Inversion is provided by the
input shift registers are applied to gated bus drivers for
output gate
sequence formatting Prior to application to the gated bus
b. Receive Register
drivers, the output of the second word register is applied
(1) General The function of the receive
to a delay register This permits double-word input
processing without interferring with the loading of
register is to process encoder and uhf receiver-
formatted words into the output shift register Word length
transmitter output data during BITE operation The
for purposes of processing the various data is
circuitry is located on video Interface module 2A17 and
determined by dividing a 625 kHz input clock by 15, and
output buffer mod-ule2A12(fig 2-11)
(2) Functional description During the first
using the resultant 41 667 kHz to cycle a word
counter/interrupt logic network The timing and control
phase of BITE operation, the data output of the encoder
circuitry is started by the RESET signal
is serially loaded into the receive shift register through
(3) Preamble formatting Preamble words
selector circuitry Selector control, in turn, is enabled by
are the first words transmitted and require no
the TEST ENC signal, which transitions high during the
modification to their bit structure During preamble, the
period the encoder output is to be sampled When TEST
word counter logic is preset to a count of eight When a
ENC transitions low, the output of the uhf receiver-
count of 15 is reached, a signal is applied to the timing
transmitter is selected for application to the receive shift
and control logic, in preparation for loading of the
register Prior to application to the receive register, the
th
transmit shift register, which occurs on the next (16 )
uhf receiver-transmitter output undergoes amplification
th
clock cycle During the 16 clock cycle, the first word
The receiver shift register is clocked using a submultiple
input register (being previously enabled) is parallel
of the 625 kHz signal received from the internal clock
loaded into the output shift register (via the preamble
gated bus driver) At the same time, the delay register is
performed by a 1-of-8 decoder circuit After a complete
enabled, so that on the next word count the data from
data word (11 bits) is loaded into the shift register, the
the second word input register is parallel loaded into the
data is sequentially transferred to the data bus, in 8-bit
output shift register During the second word count, the
increments, for processing by the CPU The data transfer
first word data is serially outputted by the output shift
is accomplished by respective tristate octal data latches
register Upon output shifting of the word from the second
As a first step, simultaneous clocking of the first and
word register, an XMIT REG interrupt is generated, at
second word latches is enabled by operation of the
which time the next two preamble words are loaded into
timing and control logic The respective clock inputs are
the output format generator As a final processing step,
de-rived from the word counter and frequency divider
the serial output data is applied through an output gate
logic Once the data is latched, sequential gating of each
which performs polarity inversion on alternate words for
octal data latch occurs, at which time the data is
purposes of polarity equalization
transferred to the data bus The first 8-bit word to be
(4) Radar mode and ADAS formatting
transferred contains the low order bits and is clocked out
Following transmission of preamble data, radar mode
in conjunction with signals 2006 and RC The second
and ADAS data are generated Processing in these
word, which contains the high order bits, is clocked by
cases, how-ever, is modified by the addition of three
signals 2008 and RC The receive shift register is
parity bits to each 8-bit word, and presetting of the clock
initialized on the negative transition of RESET
counter to a count of five The parity scheme involves
generating an odd parity bit for the high and low order
2-16. Power Supply and Distribution Functional
four bits of each data word, and then generating a third
Description
parity bit based on the status of the high and low order
parity bits With the inclusion of parity bits, the mode and
Primary power consisting of 115 V ac, 400 Hz (single
ADAS data, in final form comprising 11-bit words, is
phase) and +28 V enters the encoder and is applied to
parallel loaded into the output shift register and serially
EMI filter FLI From Fll, the +28 V is applied to
transmitted in a manner similar to the preamble data
Again, processing is performed in two word groups, while
alternate word polarity inversion is provided by the output
gate .
(5) MT and FT video formatting Following
transmission of mode and ADAS data, the MT and FT
video data is transmitted Although the MT and FT word
2-18
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