TM 11-5841-287-30
and the address data bus is available for general use
made, the MPU proceeds to generate an address
VALID MEMORY ADDRESS (VMA)-Thls output signal
corresponding to the particular function as follows 200A
indicates that a valid address is present on the address
(drift angle), 2004 (ADAS), 2008 (receive register), 0006
buq and Is used in conjunction with other signals (R/W
and 0007 (transmit register) In the case of drift angle,
and 02) to gate data and outputted by the
ADAS and receive register, the address functions are
microprocessor
used to gate formatted data onto the data bus for storage
READ/WRITE (RW)-This output signal indicates whether
in the output memory The transmit register address
the microprocessor is in a read (high) or write (low) state.
functions (0006 and 0007) are used to control transfer of
2-The falling edge of this internally generated
data from the data bus to the output format generator
The receive register, furthermore, is addressed only
microprocessor clock transfers data between the
during a BITE sequence and only in conjunction with a
microprocessor and peripheral devices
transmit register interrupt If at any time a second
OUTBUF IRQ (OUTPUT BUFFER INTERRUPT
interrupt is received while an existing interrupt sequence
REQUEST)-This input requests that an interrupt
is in progress the second interrupt is stored for the
sequence be started Start of the interrupt sequence is
remainder of the existing sequence, and then processed
delayed until completion of the current instruction NMI
accordingly
(NONMASKABLE INTERRUPT)-This input signal
e. Gated Bus Driver Logic During normal
(normally high) transitions low to request that a
operation, the microprocessor is periodically updated,
nonmaskable interrupt sequence be started by the
with various status and operational data, using gated bus
microprocessor As with the OUTBUF IRQ signal, the
driver logic for interface purposes The information is
microprocessor completes execution of the current
inputted to the microprocessor via the data bus Antenna
instruction before recognizing the NMI signal
transition detect status, B/C field select status and video
c. Data Bus Transceivers Transfer of data
data transfer (HALT) status are derived from the video
(DO-D7) to and from the microprocessor is
data processing section and inputted to the
accomplished through data bus transceivers Directional
microprocessor in the D7, D6 and DI bit positions,
control of the data bus transceivers is dependent on the
status of signals BA, VMA, R/W and 2, as monitored by
respectively Receiver-transmitter operational status is
derived from the uhf receiver-transmitter and inputted to
the control logic When BA transitions high, a low enable
the microprocessor in the D5 bit position, a one
level is applied to the data bus transceivers, thereby
representing a detected sync or power malfunction
preventing MPU from the writing of data and making the
Encoder transmit/standby status is derived from the data
data bus available for other sections The MPU address
link control and inputted to the microprocessor in the D2
signals (AO through All and A15) to the output memory
position, a one represents standby and a zero represents
are applied through address bus drivers Control of the
transmit mode BITE request status is also derived from
address bus drivers is dependent on the status of signal
the data link control, with signal latching performed prior
BA, as monitored by the control logic Enabling of the
to application to gated bus driver logic Separate downlink
address bus drivers (via a low level) occurs while the BA
BITE and airborne BITE requests are generated,
line is low
airborne BITE request is inputted to the microprocessor
d. Interrupt Detection Logic Interrupt sequence
in the D3 bit position, while downlink BITE request is
are initiated by the interrupt detection logic upon sensing
inputted in the D4 bit position Gated bus driver is
an interrupt request in the form of a low level transition
enabled by signals 2000 and RC Left/right antenna
on any of four interrupt lines The four basic interrupts are
status is received from the video data processing section
ADAS RDY (ADAS data ready), CLEAR (drift angle data
by a second gated bus driver network and inputted to the
ready), RT DATA ERROR, and XMIT REG (transmit
microprocessor in the D1 position In this case, a one
register empty) MPU notification of an interrupt request is
(high) represents right antenna and a zero (low)
enabled by high level transition of the OUTBUF IRQ line
represents left antenna This gated bus driver is enabled
In response to the interrupt request, the MPU outputs
by signals 2002 and RC
hexadecimal address 2002 on the address bus, which is
Synchronous Control Signal Logic In
f.
returned to the interrupt detection logic (via the hardware
addition to receiving status information in the form of
address decoding logic) in decoded form as signal 2002
synchronous data, the microprocessor outputs
At the MPU interrupt detection logic, signal 2002 is gated
with 2 and RC, the resultant of which is used to clock
synchronous control signals Interface between the data
bus and user circuits is accomplished through a series of
interrupt source data onto the data bus for readout by the
binary latches Signals for controlling the encoder BITE IN
MPU The specific data bits used for identification of the
PROCESS indicator (EN BIPL) on the data line control
interrupt sources are D3 (RT DATA ERROR), D4
and resetting the video data processing cir-
(CLEAR DRIFT ANGLE), D6 (ADAS RDY) and D7 (XMIT
REG)
Once
interrupt
identification
is
2-14
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