TM 11-5841-287-30
cuitry (INT RES) and BITE request latches (BTR RES)
in support of related data processing operations Signals
are generated as a function of data bits DO, D4 and D5,
OXXX, BA, WC, All, A15 and are applied to the output
respectively Latch clocking is enabled by signals 0000,
memory section, while the output format generator and
WC and AO To activate the BITE IN PROCESS
receive register section receives signals RC, WC, 0006,
0007, 2006 and 2008 Drift angle input data processing is
indicator, the EN BIPL line is set high, resulting in lamp
enabled by signals RC, WC, AO, 0000 and 200A, while
conduction via the BITE LITE line Resetting of the video
signals RC, 2008 and AO are utilized for range and
data processing circuitry and BITE request latches is
range delay input data processing Signals utilized for
enabled by setting the INT RES and BTR RES lines low
ADAS input data processing include WC, RC, 0002,
Signals for controlling the ENCODER and R/T FAULT
2002 and 2004, while synchronous gating of ground
indicators (on the data link control), and for multiplexing
speed input data is provided by signals 200B-EN and
associated with selection of BITE references sources
200C-EN, which are generated from signals RC, AO,
(BITE, B-FT, B-MT), are generated as a function of data
200A and 200C
bits DO, D6 and D7, respectively Latch clocking is
i. MPU Reset The master reset line (RESET) is
enabled by signals RC and 0002 Illumination of the
ENCODER and R/T FAULT indicators (as a result of
driven low following power turn-on and when the
BITE, power supply or R/T sync failure) is enabled
microprocessor falls to recycle within normal time lim-its
similar to illumination of the BITE IN PROCESS
(MPU lock-up) The power-on reset time lasts ap-
indicator, with respective lamp drive provided via the
proximately 28 milliseconds (ms) and is a function of
ENCDR ERROR and R/T LITE lines Setting the BITE
frequency counting and R-C delay time An 83 Hz signal
line high results in substitution of BITE data in place of
serves as the basis for frequency counting If MPU lock-
normal system data Simulated FT and MT video signals
up occurs, as evidenced by absence of transitions on the
are introduced by setting the B-FT and B-MT lines high
OUTBUF IRQ line, a timeout sequence is initlated,
Signals for defining unit under test (TEST ENC), for
utilizing the 3 Hz signal After eight cycles (2 6 sec) have
resetting the antenna transition detection circuit, and for
elapsed, the RESET line is automatically driven low to
definition of the both antenna mode of operation (BOTH
reset the encoder circuitry
ANT) are generated as functions of data bits D3, D5 and
D4, respectively Latch clocking is enabled by signals RC
2-14.
Output Memory Section
and 0004 Setting the TEST ENC line high results in test
data monitoring at the output of the encoder, while a low
a. General The function of the output memory
level results in test data monitoring at the output of the
is to provide temporary storage of the variable radar data
encoder, while a low level results in test data monitoring
periodically transmitted downlink and permanent storage
at the output of the uhf radio set Setting the RESET XTN
of the preamble and MPU program code The radar data
DET line high starts the antenna transition detector in the
transmitted within each frame consists of one mode
video data processing section Following four successive
word, 48 ADAS words and 1120 video words The
detected antenna transitions, the BOTH ANT line is set
variable data is stored in random access memory (RAM),
high to provide notification to the video data processing
while all fixed data is stored in read only memory (ROM)
section of recognition of the both antenna mode of
The output memory circuitry is located on output memory
operation
module 2A14 Figure 2-10 provides block diagram details
g. Error Source Signals Error source definition
b. Data Bus Transceivers Two-way interface
signals are provided to aid in performing troubleshooting
with the system data bus is provided by the data bus
when BITE performance results in a fault indication The
transceivers Directional control of the data bus
error source signals consist of OUTPUTIRECV IRF, for
transcelvers is provided by the control logic in
an output or receive register fault, ADAS IRF, for an
accordance with control signals RC (read control), OXXX
ADAS data processing fault, VID "A", for a A-field video
and BA (bus available) Transfer of data into memory
fault, VID "B", for a B-field video fault, VID "C" for a C-
occurs when the RC line transitions high, at which time
field video fault, FILM SPD, for a film speed data
I/O SELECT input to the data bus transceivers
processing fault, DRIFT ANG, for a drift angle data
transitions low Transfer of data onto the data bus occurs
processing fault, and R/T (DATA), for an R/T data fault
when RC, OXXX and BA transition low, at which time
The error source signals are generated as functions of
I1O SELECT transitions high
data bits DO-D7, respectively Latch clocking in this case
c. Data Reading/Writing Two configurations
is enabled by signals WC and 0000
exist for writing data into memory One configuration is
h. Hardware Addressing In addition to being
used for writing the video data outputted by the video
used within the CPU section, a variety of control and
processing section The other configuration is used for
address functions are distributed throughout the encoder
writing into memory the remaining variable radar
2-15
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