TM 11-5841-287-30
successive pulses The converted data, represented by
main output program instructions In the case of
two successive 8-bit data words (only 12 bits of which
preamble data, no modification or addition to the data
are used), is then transferred (via the data bus) to output
word bit structure is required, while mode and ADAS
RAM under CPU control
words require addition of three parity bits, resulting in a
e. Drift Angle Input Data Processing Substitute
final format of 11 bits The video data is also modified
from 8-bit to 11-bit format, however, the additional bits
aircraft drift angle input data (VERT SWP) is received in
are obtained by simple redundant connections at the
the form of an analog signal The slope of the VERT
inputs of the respective registers
SWP signal varies in direct proportion to the vertical
Receive Register The purpose of the receive
i.
sweep signal in the radar recorder This permits drift
register is to provide initial processing for the RCVR data
angles to be measured regardless of the selected aircraft
outputted by the receiver section of the uhf receiver
navigation mode (inertial or manual) Similar to the video
transmitter This processing operation, part of the online
data processing, analog-to digital conversion is
BITE provided by the encoder, is performed whenever
performed prior to data transfer to the output RAM.
f.
Central Processing Unit Data processing
data is being transmitted to the ground station. Upon
accumulation of 11 data bits (one data word), the receive
operations, with the exception of video input data
register data is clocked onto the data bus for transfer to
processing, are under CPU/program control The
the CPU section where it is checked for proper
respective programs are permanently stored m the read-
synchronization The period during which the data words
only memory (ROM) portion of the output memory
are checked begins at ADAS and concludes at the start
section. The program Instructions are executed by the
of video Should improper data synchronization be
CPU microprocessor, which transfers data via 8 parallel
detected, a uhf receiver-transmitter fault indication is
data lines and accesses memory locations via 16 parallel
registered on the data link control
address lines CPU timing and synchronization are
j.
Power Distribution and Control The encoder
provided by a clock derived from the internal clock
receives 115 V ac, 400 Hz single-phase and 28 V dc
generator During the output transmit cycle, the CPU
primary power from the aircraft The 115 V ac is used
transfers data from the output memory to the output
primarily for generation of regulated 12 V dc and + 5 V
format generator where final data formatting is
dc transistor supply voltages The 28 V dc is used for
performed prior to downlink transmission During operator
relay control and data link control indicator power. Power
initiated BITE, control signals are received from the data
supply operational status is continuously monitored by
link control, via the BITE control/display interface, for
power fault detection circuitry. Should any voltage
selection of the airborne and downlink BITE modes of
exceed or drop below normal limits, power fault error (PF
operation BITE display signals are outputted to the data
ERROR) is applied to the data link control, to illuminate
link control for BITE in-process and failure display.
g. Output Memory The output memory section
the ENCODER FAULT indicator
k. Data Link Control In addition to providing
consists of random access memory (RAM), read only
BITE control/display facilties, the data link control
memory (ROM), and associated interface and control
provides selection of off, standby, and transmit modes of
circuits The RAM is used for storage of the variable data
operation With respective selector switch set to off, all
transmitted each frame to the ground station The ROM is
system functions cease In the standby mode of
used for storage of the fixed program code, which
operation, the system is energized, with the exception of
defines the repetitive operational sequences related to
the transmitter section in the uhf receiver-transmitter
the processing, transfer, and formatting of data The
BITE testing during standby operation is limited to the
interface circuitry consists of bidirectional networks used
encoder In the transmit mode of operation, the system is
for transfer of data to/from memory, depending on the
fully operational BITE testing in the transmit mode
control logic status Should encoder power supply failure
encompasses both the encoder and uhf receiver-
occur at any time during normal operation, encoder fault
transmitter.
indication is provided. In this case error display is
enabled by activation of the power fault error (PF
ERROR)
line
Should
uhf
receiver-transmitter
2-6.
Encoder Programs
synchronization or low rf power failure occur at any time
The majority of data processing, transfer, and formatting
during normal operation, uhf receiver-transmitter fault
is done by four programs main-output, hardware
indication is provided. In this case, error display is
interrupt, housekeeping, and BITE
enabled through activation of the uhf receiver-transmitter
a. Main Output/Hardware Interrupt Programs
malfunction (RT MALF)
The /main-output program uses CPU interrupt circuitry to
line outputted by the uhf receiver-transmitter
generator organizes the data to be transmitted into a
serial bit stream through operation of various registers
and associated counting and control logic The data is
processed in two word groups in accordance with the
2-6
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