TM 11-5841-287-30
(FILM SPEED) The CPU section (para 2-13) receives 4
and video multiplexer module 2A9 b Input Amplification
MHz (XTAL), which serves as the microprocessor clock,
and Conditioning The MT and FT video input signals
and 3 Hz and 83 Hz signals, which are used for purposes
initially undergo amplification and conditioning on video
of MPU lockup and power-on-reset generation During
interface module 2A17.
Additional amplification on
special test equipment (STE) operations, the 20 MHz
module 2A17 provides conditioning of the 5 MHz GTD
internal oscillator signal is replaced by a 5 MHz STE
CLOCK and ANTEN-NA GATE input signals The
clock signal (STE CLK) Selection between the internal 20
amplified MT and FT video signals, which are adjusted
MHz signal and the STE CLK signal is provided by the
for a maximum level of +4 5V, are applied to respective
STE CLK SEL signal Periodic resetting of the frequency
analog-to-digital converters located on A/D converter
divider logic during STE operation is enabled by the STE
module 2A2 The conditioned 5 MHz GTD CLOCK and
RESET signal During BITE operation, signal INT RESET
ANT SELECT signals are applied as inputs to the video
transitions low to initialize the B GTD 5 MHz signal
timing and control logic on video control module 2A7
c. Analog-To-Digital (A/D) Conversion The MT
A/D converter samples the input video signal at a 200 ns
2-8.
Video Input Data Processing Section
(5 MHz) rate, providing a 3-bit output data word
representative of video magnitude Since the required
a. General The function of the video data
sample rate of 5 MHz exceeds the upper frequency limit
processing circuitry is to convert the FT and MT video
of the temporary (accumulator) memory to be used for
inputs to digital form for serial transmission downlink.
storage of the A/D data, a dual data processing network
Two basic operations are associated with video data
is used Essentially data from all odd range cells is
processing, data accumulation and data transfer. During
processed by one network, while a similar network
data accumulation, the video data undergoes amplitude
processes data from all even numbered range cells By
averaging over a fixed number of radar pulse repetition
dividing the data processing function in this manner, the
intervals (PRI) for each of 1680 range cells The range
individual network processing rate is reduced to 2 5 MHz,
cells are grouped into three equal fields of 560 each,
which is within the operating range of the accumulator
designated A, B and C, A-field being closest to the
memory elements Operation of the FTA/D converter is
aircraft The averaging period for A-field is 256 PRI, while
similar to the MTA/D converter except that FT magnitude
B/C-field averaging is performed over 512 PRI
resolution is expressed in the form of a 5-bit data word
(Averaging over twice the A- field rate is possible due to
for each A/D sample Expressed as a function of voltage,
widening of the radar beam width as the range from the
MT threshold resolution is approximately 0 57V (7 X 0
antenna increases ) Input data, during data
57V - 4V), while FT threshold resolution is approximately
accumulation, is sampled at a 5 MHz rate, using a gated
0 129V (31 X 0 129V - 4V)
5 MHz clock signal supplied by the external equipment
d. Video Accumulator Memories Following A/D
Since the upper frequency limitation of the accumulator
conversion the FT data is applied directly to
memory is less than 5 MHz, accumulation is performed
corresponding odd and even accumulator memories
by two separate networks, each operating at a 2 5 MHz
(located on modules 2A3 and 2A4), while the MT data is
rate Essentially, data from all odd numbered range cells
routed to odd and even MT accumulator memories
is accumulated by one network, while the other is used
(located on modules 2A5 and 2A6) via a magnitude
for accumulation of data from all even numbered range
comparator/selector network (located on video
cells When accumulation is complete, average values
multiplexer module 2A9) During single antenna (left or
are computed for each range cell Before transfer to the
right) operation, the odd and even MT data is switched
output memory section, special processing Is also
directly through the magnitude comparator/selector
performed whereby weaker targets receive enhancement
During both antenna (left and right) operation,
by selective bit allocation During the data transfer period,
comparison of adjacent range cell data is performed The
the accumulated data for each range cell is transferred
larger of the MT target data, whether odd or even, is then
to the output memory section (via control of the video
applied to modules 2A5 and 2A6 via both the odd and
control board) for storage prior to downlink transmission
even MT data lines This feature Insures retention of the
A 1 25 MHz clock rate is utilized during data transfer
primary MT target since, during both antenna operation,
operations The 1 25 MHz clock is generated internally
left antenna data is stored exclusively in the even MT
and is asynchronous to the externally derived gated 5
accumulator memory, while right antenna data is stored
MHz clock signal The video data processing circuits are
exclusively in the odd MT accumulator memory The
located on video interface module 2A17, analog-to-digital
accumulation period for A-field data is 256 PRI, while the
(A/D) converter module 2A2, video control module 2A7,
B/C-field accumulation period is 512 PRI
FT accumulator memories 2A3 (odd) and 2A4 (even),
MT accumulator memories 2A5 (odd) and 2A6 (even),
2-8
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