TM 11-5841-287-30
The accumulated MT data magnitude is expressed in the
conveyed to the CPU via the ANT XTN DET line, which
form of a 12-bit data word, while FT data magnitude is
is set high every time antenna switching occurs Periodic
expressed in the form of a 14-bit data word Operation of
resetting of the antenna transition detection logic on
the MT and FT accumulator memories is similar with the
module 2A7 is enabled by the XTN DET RESET line,
exception of range cell address count- ing, which is
which is reset (low) after acknowledgment of antenna
performed on the MT accumulator memory boards for
transition detection by the CPU Read/write control of the
use on both MT and FT accumulators When data
accumulator memory elements is enabled by signals
accumulation is complete, the contents of the
R/W-O and R/W-E, which transition low for writing data
accumulator memories are unloaded, address by
mto accumulator memory and transition high for reading
address, for final processing before storage m the out-
data out of accumulator memory during data transfer
put memory.
HALT transitions low to signify start of the video data
Output Data Processing/Selection Final
e.
transfer period, during which time the microprocessor in
the CPU section is disabled Should ADAS input data be
processing of the accumulated MT and FT data is
received during video data transfer, the ADAS DISABLE
accomplished by the output data processing/selection
signal transitions low, at which time additional video data
circuitry (located on video multiplexer module A9) During
transfer ceases until the present ADAS input data is
final processing, average values are computed for each
processed into memory Upon completion of ADAS in-
odd and even range cell The data then undergoes further
put data processing, ADAS DISABLE returns to a high
processing to enhance the weaker targets with- out
level and video data transfer resumes Avail- ability of the
increasing overall bandwidth usage Specific pro- gram
data bus for transfer of video data is determined by
selection is a function of operating mode and field status
sensing the VID BA signal level, which transitions high
Mode decoding is accomplished by sensing the level on
when the data bus is available for video data transfer
the BOTH ANT line, which is high during both antenna
Signal IWC transitions low to indicate to the output
operation, and on the AB/C line, which transitions high
memory that valid video data is warning to be loaded
during B and C field periods The resultant output data,
Generation of the IWC signal is enabled by the gating of
whether MT or FT, is expressed In 8-bit format The MT
the 1 25, 2 5, and 5 MHz internal clock signals During
data consists of three data bits, three error correcting
data transfer, master tim- ing is derived from the 1 25
(Hamming code) bits, and two identification (ID) bits FT
MHz clock supplied by the internal clock generator
data consists of five data bits, two ID bits, and one parity
Consequently, the contents of the accumulator
bit The data format is as follows:
memories are read out at one- fourth the accumulation
D7 D6 D5 D4
D3
D2
D1 DO
rate, in conjunction with clock signals RAOO and RAOE
FT=FT4 ID FT3 FT2 FT1 FTO
ID P
The signal INT RES, from the CPU section, resets the
MT=MT2 ID MT1 MTO H2
H1
ID HO
timing and control circuits g Video BITE BITE operation
The selected output data (MT or FT) depends on the MT
commences follow- ing transition of the BITE lihne to a
data magnitude When the MT data magnitude is greater
high level In the BITE mode of operation, time varying
than a fixed reference magnitude, indicating a true MT
test signals (MT BITE VID and FT BITE VID) are
target, MT data is transferred to the output memory for
substituted in place of the normal MT and FT VIDEO
downlink transmission When the MT data magnitude is
signals Test voltage generation is enabled by signals B-
less than the reference magnitude, FT data is selected
FT, B-MT, RA5E and RA6E During video accumulation,
for transfer to the output memory
f.
Timing and Control Timing and control
signals RA5E and RA6E cause certain range bins to
integrate (synchronously) to predetermined fixed voltage
during data accumulation and transfer is enabled by
levels Signals B-FT and B-MT appear as fixed or
circuitry located on video control module 2A7 During data
switching levels, depending on the BITE sequence m
accumulation, the A/D converters receive timing signals
progress During airborne BITE, the signals are fixed at a
ADLO and ADLE for latching each data sample The MT
high level Following completion of three video integration
and FT accumulator memories receive signals ADLO
cycles, data checks are performed for selected A, B, and
and ADLE for latching each data word out- putted by the
C field values, in conjunction with high and low limit
A/D converters Summing over the averaging periods for
reference levels stored in the output memory ROM
each range cell is enabled by clock signals RAOO and
During downlink BITE, signals B-FT and B-MT are varied
RAOE, which are derived from the GTD 5 MHz CLOCK
for purposes of generating a predetermined image on
input, at one-half the input clock rate (2 5 MHz) Circuitry
the ground station recorder It should also be noted that
for counting the radar pulse repetition mtervals is
during BITE operation, an internally generated gated 5
enabled by the LOAD signal, while signals MT DAINLAR,
MHz
reference
clock
(B-GTD
5
MHz)
is
FT DAINLAR and R CLEAR provide periodic resetting of
the accumulator memory logic Antenna mode status is
2-9
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